Paweł Spychalski
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95f3913491
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Update README.md
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2018-08-17 13:33:26 +02:00 |
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kadrim
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7b47d02315
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added dependency for FlashStorage if using a SAMD-Board
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2018-07-10 10:13:04 +02:00 |
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Pawel Spychalski (DzikuVx)
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85fd50d8bf
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Readme update
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2018-05-31 17:56:24 +02:00 |
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Pawel Spychalski (DzikuVx)
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8bb2a403c5
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Docs for binding
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2018-05-31 16:01:24 +02:00 |
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Pawel Spychalski (DzikuVx)
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c7f5f4f8bb
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work
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2018-05-21 21:19:23 +02:00 |
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Pawel Spychalski (DzikuVx)
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f884b5e70c
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All other static OLED pages
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2018-05-21 15:16:28 +02:00 |
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Pawel Spychalski
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8bef083c0a
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docs update
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2018-05-07 13:55:15 +02:00 |
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Pawel Spychalski
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ce1586a667
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updated docs
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2018-05-02 13:41:40 +02:00 |
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Pawel Spychalski (DzikuVx)
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e22012ce6d
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Docs update
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2018-04-29 20:53:15 +02:00 |
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Pawel Spychalski (DzikuVx)
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b211a4a2b6
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Bind key used to init frame CRC
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2018-04-26 21:29:52 +02:00 |
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Pawel Spychalski (DzikuVx)
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f1029051f4
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updated docs
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2018-04-20 21:14:43 +02:00 |
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Pawel Spychalski (DzikuVx)
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52daef7667
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TX module diagram
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2017-11-19 13:46:50 +01:00 |
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Pawel Spychalski
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9f48e0fd6f
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Updated CRC method
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2017-11-15 18:56:11 +01:00 |
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Pawel Spychalski
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1057c0995c
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protocol preamble removed as not required for LoRa packet processing
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2017-11-09 14:56:59 +01:00 |
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Pawel Spychalski
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47f9a37270
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diagram for RX module
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2017-11-07 13:14:31 +01:00 |
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Pawel Spychalski (DzikuVx)
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0f735f0054
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close #23
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2017-10-27 11:25:48 +02:00 |
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Pawel Spychalski (DzikuVx)
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9ea446de79
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Slots for transmitting on RX side close #8
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2017-10-26 20:03:20 +02:00 |
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Pawel Spychalski (DzikuVx)
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a800031b0a
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close #15
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2017-10-26 13:51:34 +02:00 |
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Pawel Spychalski (DzikuVx)
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08b16b4cea
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close #6
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2017-10-22 11:56:17 +02:00 |
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Pawel Spychalski
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021decff98
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Rx_health frame encoding, no data is yet acquired from Rx hardware
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2017-10-12 13:29:10 +02:00 |
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Pawel Spychalski (DzikuVx)
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4bc7668ae9
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Support for SPI connected SX1278
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2017-09-30 18:43:03 +02:00 |
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Pawel Spychalski (DzikuVx)
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8c3199a60f
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readme update
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2017-09-30 16:21:52 +02:00 |
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Pawel Spychalski (DzikuVx)
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66a88259f9
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docs update
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2017-09-27 20:39:43 +02:00 |
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Pawel Spychalski (DzikuVx)
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b338ba959a
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RC_DATA frame encoded
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2017-09-24 12:05:21 +02:00 |
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Pawel Spychalski (DzikuVx)
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02667929c0
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another protocol update
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2017-09-23 15:57:18 +02:00 |
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Pawel Spychalski (DzikuVx)
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e07b045cbe
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Channel ID added to protocol
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2017-09-23 15:46:54 +02:00 |
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Pawel Spychalski (DzikuVx)
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cac6172d06
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RC_DATA protocol frame updated
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2017-09-23 10:50:15 +02:00 |
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Paweł Spychalski
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fc088ae764
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Update README.md
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2017-09-22 22:36:24 +02:00 |
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Paweł Spychalski
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bbd02ef713
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Initial commit
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2017-09-22 21:05:20 +02:00 |
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