Pawel Spychalski (DzikuVx)
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86c7c3af0a
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Small optimization
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2017-10-29 09:56:06 +01:00 |
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Pawel Spychalski (DzikuVx)
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0f735f0054
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close #23
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2017-10-27 11:25:48 +02:00 |
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Pawel Spychalski (DzikuVx)
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86f70accff
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TX module is no longer using interrupts to read from LoRa. This fixes jumpy PPM readouts
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2017-10-27 07:20:43 +02:00 |
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Pawel Spychalski (DzikuVx)
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9ea446de79
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Slots for transmitting on RX side close #8
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2017-10-26 20:03:20 +02:00 |
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Pawel Spychalski (DzikuVx)
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a800031b0a
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close #15
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2017-10-26 13:51:34 +02:00 |
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Pawel Spychalski (DzikuVx)
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429d808fa2
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close #10
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2017-10-25 21:18:01 +02:00 |
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Pawel Spychalski (DzikuVx)
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d0120405fb
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close #17
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2017-10-23 19:37:13 +02:00 |
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Pawel Spychalski (DzikuVx)
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974a31ad61
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Fixed missing constrain
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2017-10-23 19:24:50 +02:00 |
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Pawel Spychalski (DzikuVx)
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0a1b5feecd
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close #1
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2017-10-22 20:14:28 +02:00 |
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Pawel Spychalski (DzikuVx)
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08b16b4cea
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close #6
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2017-10-22 11:56:17 +02:00 |
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Pawel Spychalski (DzikuVx)
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779b64189a
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close #2
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2017-10-22 09:31:46 +02:00 |
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Pawel Spychalski (DzikuVx)
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d790d087fe
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Fixed debug flags
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2017-10-20 23:06:14 +02:00 |
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Pawel Spychalski (DzikuVx)
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810abc14eb
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Fixed SPI mode with LoRa32u4 II
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2017-10-20 22:47:46 +02:00 |
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Pawel Spychalski
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021decff98
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Rx_health frame encoding, no data is yet acquired from Rx hardware
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2017-10-12 13:29:10 +02:00 |
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Pawel Spychalski
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0071b7880f
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Store last time frame was received
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2017-10-12 10:45:14 +02:00 |
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Pawel Spychalski
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ff2f0f710a
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RX failsafe with pulling PPM output LOW
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2017-10-11 14:40:17 +02:00 |
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Pawel Spychalski (DzikuVx)
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01836b8657
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another small refactoring
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2017-10-07 19:06:07 +02:00 |
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Pawel Spychalski (DzikuVx)
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022f186175
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quite major overhaul
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2017-10-07 18:57:13 +02:00 |
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Pawel Spychalski (DzikuVx)
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3deec452ef
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refactoring
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2017-10-07 14:53:50 +02:00 |
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