david.tahir/QuadMeUp_Crossbow
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Author SHA1 Message Date
Pawel Spychalski (DzikuVx)
9e18e5377c Lowered RSSI audible alarms 2018-04-28 21:39:51 +02:00
Paweł Spychalski
0f0dbf6cb3 Merge pull request #53 from DzikuVx/tx-indication-improvements 
TX module LED indication
 2018-04-28 08:06:16 +02:00
Pawel Spychalski (DzikuVx)
3ea77891f1 TX module LED indication 2018-04-27 23:05:44 +02:00
Paweł Spychalski
e66b883137 Merge pull request #51 from DzikuVx/feature/crc-with-salt 
Feature/crc with salt
 2018-04-27 22:11:46 +02:00
Pawel Spychalski (DzikuVx)
14d8215543 Fixed bind key crc salting 2018-04-27 22:03:20 +02:00
Pawel Spychalski (DzikuVx)
b211a4a2b6 Bind key used to init frame CRC 2018-04-26 21:29:52 +02:00
Pawel Spychalski (DzikuVx)
76d4f7d70b hardcoded 4 byte binding key 2018-04-26 19:52:46 +02:00
Pawel Spychalski (DzikuVx)
f1029051f4 updated docs 2018-04-20 21:14:43 +02:00
Pawel Spychalski (DzikuVx)
f677d902d3 updated RSSI indication on RX side 2018-04-19 18:34:56 +02:00
Pawel Spychalski (DzikuVx)
a651fcc05e imporved sbus input handling on TX module 2018-04-19 16:24:17 +02:00
Paweł Spychalski
4cae36715d Merge pull request #49 from DzikuVx/feature/frequency-hopping 
Frequency hopping -> second attempt
 2018-04-19 16:07:33 +02:00
Pawel Spychalski (DzikuVx)
956fe00ccb Syncing improvements 2018-04-19 16:06:54 +02:00
Pawel Spychalski (DzikuVx)
feeeb78105 Sync RX and TX 2018-04-19 15:40:36 +02:00
Pawel Spychalski (DzikuVx)
12e2bca441 Fixed current channel indication and next channel computation 2018-04-19 12:49:40 +02:00
Pawel Spychalski (DzikuVx)
b6814509a2 Merge branch 'master' into feature/frequency-hopping 2018-04-19 11:51:35 +02:00
Pawel Spychalski (DzikuVx)
66693914d1 improed processing of sbus frames 2018-04-19 11:18:36 +02:00
Pawel Spychalski
f1e659bfd0 Happy path frequency hopping 2018-04-10 15:01:27 +02:00
Pawel Spychalski
6ee2caf68d new features ported from Arduino-LoRa library 2018-04-10 10:29:53 +02:00
Pawel Spychalski
2ebdf6df88 ensure pin DIO0 is set to input 2018-04-10 10:14:21 +02:00
Pawel Spychalski
17196725c1 updated SNR registry 2018-04-10 10:12:11 +02:00
Paweł Spychalski
886af488ea Merge pull request #48 from DzikuVx/feature/hardcoded-frame-length 
frame payload lengths is now const. depending on frame type
 2018-04-10 09:34:51 +02:00
Pawel Spychalski
4ec1525659 frame payload lengths is now const. depending on frame type 2018-04-10 09:17:46 +02:00
Pawel Spychalski
db1cd344cb some config optimizations 2018-04-10 08:53:15 +02:00
Pawel Spychalski (DzikuVx)
b38dc15ba5 changed default input protocol 2018-04-02 20:52:56 +02:00
Paweł Spychalski
cf056fb528 Merge pull request #47 from unitware/conditional-ppm-input-on-tx 
Hardware and configuration selections and travis build server setup
 2018-02-12 15:48:13 +01:00
Magnus Ivarsson
64e05f911a ignore some ppm files to avoid mistakes 2018-02-11 20:10:43 +01:00
Magnus Ivarsson
d07a8a09d3 travis build 
different configurations are specified in the configurations directory
 to select one copy it replcing the config.h file (as the travis script does)
 or change the include file directive in crossbow.ino
 2018-02-11 19:41:00 +01:00
Paweł Spychalski
2ac0ce9b49 Merge pull request #42 from DzikuVx/channel-processing-speedup 
Processing speedup
 2018-01-03 20:21:32 +01:00
Pawel Spychalski (DzikuVx)
f75a8f8d7b Fixed serial on TX 2018-01-03 20:20:40 +01:00
Pawel Spychalski (DzikuVx)
c61a87361e Merge branch 'master' into channel-processing-speedup 2018-01-03 19:44:44 +01:00
Paweł Spychalski
34744ac5d7 Merge pull request #35 from DzikuVx/tx-sbus 
SBUS support on TX module
 2018-01-03 19:43:02 +01:00
Pawel Spychalski (DzikuVx)
365df5b269 Improved failsafe state detection when TX module is not receiving input 2018-01-03 19:41:59 +01:00
Pawel Spychalski
fbbd5fc68e Processing speedup 2018-01-03 13:32:24 +01:00
Pawel Spychalski
43e0d87dbd I2C speed bumped to 400kHz 2018-01-03 11:48:01 +01:00
Pawel Spychalski (DzikuVx)
55964dc330 Merge remote-tracking branch 'origin/master' into tx-sbus 2018-01-02 21:25:22 +01:00
Paweł Spychalski
9e7ef1e242 Merge pull request #41 from DzikuVx/tx-non-blocking 
Non-blocking (async) LoRa end Packet
 2018-01-02 21:21:57 +01:00
Pawel Spychalski (DzikuVx)
0c68c742b0 Merge remote-tracking branch 'origin/master' into tx-non-blocking 2018-01-02 21:21:36 +01:00
Pawel Spychalski (DzikuVx)
702a8331fe Allow for TX only when not already transmitting 2018-01-02 21:16:12 +01:00
Pawel Spychalski (DzikuVx)
cb3c510815 Further changes to async processing 2018-01-02 21:14:11 +01:00
Pawel Spychalski (DzikuVx)
8dfc41759e Another compiler warning fiuxed 2018-01-02 20:14:41 +01:00
Pawel Spychalski (DzikuVx)
8071d6ac74 Fixed compiler warnings 2017-12-28 12:05:18 +01:00
Pawel Spychalski (DzikuVx)
9d30a69b22 minor change 2017-12-24 14:06:34 +01:00
Pawel Spychalski
844955ded1 Merge branch 'master' into tx-sbus 2017-12-18 10:19:20 +01:00
Pawel Spychalski
ac36371cdb cleanup 2017-12-18 10:18:30 +01:00
Pawel Spychalski (DzikuVx)
e8f1976a2d async rx mode 2017-12-17 09:33:04 +01:00
Pawel Spychalski (DzikuVx)
a7c2e13b10 LoRa non-blocking endPacket from https://github.com/sandeepmistry/arduino-LoRa/pull/62 2017-12-16 11:08:39 +01:00
Pawel Spychalski (DzikuVx)
7e9f0fd04e close #36 2017-12-16 10:13:29 +01:00
Pawel Spychalski (DzikuVx)
85461b5d89 close #32 2017-12-16 09:50:02 +01:00
Pawel Spychalski (DzikuVx)
239d1b00e2 Merge branch 'master' into tx-sbus 2017-12-16 09:28:54 +01:00
Paweł Spychalski
42a0ff3513 Merge pull request #34 from DzikuVx/spi-improvements 
Packet reading is now down in single SPI transaction
 2017-12-16 09:26:27 +01:00