Pawel Spychalski
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3778fcd0cd
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Callback for QSP decoding
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2017-11-16 16:12:20 +01:00 |
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Pawel Spychalski
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9d609dfa77
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RX outout table moved to RxDeviceState object
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2017-11-16 13:31:29 +01:00 |
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Pawel Spychalski (DzikuVx)
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36dc76db0d
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Reworked radio handling to early reject false packets
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2017-11-15 18:53:31 +01:00 |
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Pawel Spychalski (DzikuVx)
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149aac3d70
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frequency change
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2017-11-11 22:23:58 +01:00 |
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Pawel Spychalski (DzikuVx)
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d322447290
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Updated radio properties
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2017-11-11 19:50:38 +01:00 |
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Pawel Spychalski (DzikuVx)
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8fc8c20697
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All processing moved from ISR to main loop
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2017-11-11 16:51:00 +01:00 |
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Pawel Spychalski (DzikuVx)
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6082f7f4a7
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task priority changed
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2017-11-11 14:09:14 +01:00 |
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Pawel Spychalski (DzikuVx)
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1a031aba3f
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Fixed bug thata was failing to process frames without preamble
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2017-11-09 19:52:52 +01:00 |
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Pawel Spychalski
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1057c0995c
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protocol preamble removed as not required for LoRa packet processing
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2017-11-09 14:56:59 +01:00 |
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Pawel Spychalski (DzikuVx)
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5ae986112f
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Several small fixes for potential race conditions
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2017-10-30 20:39:32 +01:00 |
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Pawel Spychalski (DzikuVx)
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3921cc245c
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Fixed casting bug on RX side that was causing failsafe to engage without specific reason
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2017-10-30 17:38:56 +01:00 |
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Pawel Spychalski (DzikuVx)
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b3d8847d86
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OLED RRSI scaling changed to dB
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2017-10-30 16:35:48 +01:00 |
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Pawel Spychalski (DzikuVx)
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34b7a42b85
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slower transmission
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2017-10-29 15:25:36 +01:00 |
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Pawel Spychalski (DzikuVx)
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b7782db478
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Audible alarms on TX side
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2017-10-29 13:08:39 +01:00 |
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Pawel Spychalski (DzikuVx)
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86c7c3af0a
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Small optimization
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2017-10-29 09:56:06 +01:00 |
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Pawel Spychalski (DzikuVx)
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a2fb5abffa
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Buzzer Single and Continous modes
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2017-10-29 09:35:00 +01:00 |
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Pawel Spychalski (DzikuVx)
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b3cac834e2
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Reduced number of SPI operations when reading RF packets
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2017-10-28 23:07:14 +02:00 |
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Pawel Spychalski (DzikuVx)
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72cb29eca2
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Speed optimization for S.Bus encoding
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2017-10-28 22:25:38 +02:00 |
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Pawel Spychalski (DzikuVx)
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7bb8544880
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optimizations for OLED
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2017-10-28 20:30:56 +02:00 |
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Pawel Spychalski (DzikuVx)
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74cb084017
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Basic buzzer framework
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2017-10-28 19:35:06 +02:00 |
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Pawel Spychalski (DzikuVx)
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9703d3144f
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Another small optimization to limit resource hogging
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2017-10-27 13:56:12 +02:00 |
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Pawel Spychalski (DzikuVx)
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6277d4cec9
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Code cleanup
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2017-10-27 13:44:01 +02:00 |
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Pawel Spychalski (DzikuVx)
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85b1dbe26d
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performance improvements
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2017-10-27 13:18:22 +02:00 |
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Pawel Spychalski (DzikuVx)
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0f735f0054
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close #23
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2017-10-27 11:25:48 +02:00 |
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Pawel Spychalski (DzikuVx)
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5c090b6868
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Fixed race condition that casued concurrent SPI operation and hunged the RX module
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2017-10-27 09:56:46 +02:00 |
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Pawel Spychalski (DzikuVx)
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86f70accff
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TX module is no longer using interrupts to read from LoRa. This fixes jumpy PPM readouts
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2017-10-27 07:20:43 +02:00 |
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Pawel Spychalski (DzikuVx)
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b50564f4bd
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Default bandwidth increased to 500kHz
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2017-10-26 20:18:02 +02:00 |
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Pawel Spychalski (DzikuVx)
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9ea446de79
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Slots for transmitting on RX side close #8
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2017-10-26 20:03:20 +02:00 |
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Pawel Spychalski (DzikuVx)
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9e0f425ee9
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Sloted approach on TX side
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2017-10-26 16:16:21 +02:00 |
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Pawel Spychalski (DzikuVx)
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a800031b0a
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close #15
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2017-10-26 13:51:34 +02:00 |
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Pawel Spychalski (DzikuVx)
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c409214de8
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updated SNR scaling
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2017-10-25 22:03:54 +02:00 |
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Pawel Spychalski (DzikuVx)
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0b04e32776
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LED blink on RX when receiving, Constant on FAILSAFE
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2017-10-25 21:34:53 +02:00 |
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Pawel Spychalski (DzikuVx)
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429d808fa2
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close #10
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2017-10-25 21:18:01 +02:00 |
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Pawel Spychalski (DzikuVx)
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8f194e3968
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close #18
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2017-10-25 20:21:13 +02:00 |
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Pawel Spychalski (DzikuVx)
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a6b5946a68
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close #12
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2017-10-24 21:08:04 +02:00 |
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Pawel Spychalski (DzikuVx)
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b1c3b36b7c
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close #20
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2017-10-24 20:09:43 +02:00 |
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Pawel Spychalski (DzikuVx)
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2a47aac573
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close #19 close #13
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2017-10-24 20:07:23 +02:00 |
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Pawel Spychalski (DzikuVx)
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474d2a9c84
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It works. More less
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2017-10-23 21:16:48 +02:00 |
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Pawel Spychalski (DzikuVx)
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d0120405fb
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close #17
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2017-10-23 19:37:13 +02:00 |
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Pawel Spychalski (DzikuVx)
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974a31ad61
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Fixed missing constrain
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2017-10-23 19:24:50 +02:00 |
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Pawel Spychalski (DzikuVx)
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1d16fdd052
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close #9
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2017-10-23 12:51:05 +02:00 |
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Pawel Spychalski (DzikuVx)
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471e532c5a
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close #16
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2017-10-23 12:45:25 +02:00 |
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Pawel Spychalski (DzikuVx)
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0a1b5feecd
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close #1
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2017-10-22 20:14:28 +02:00 |
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Pawel Spychalski (DzikuVx)
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08b16b4cea
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close #6
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2017-10-22 11:56:17 +02:00 |
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Pawel Spychalski (DzikuVx)
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779b64189a
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close #2
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2017-10-22 09:31:46 +02:00 |
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Pawel Spychalski (DzikuVx)
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7af49621fc
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Cleanup
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2017-10-21 08:48:23 +02:00 |
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Pawel Spychalski (DzikuVx)
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dcc1a0da34
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OLED moved to TX module
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2017-10-21 08:21:30 +02:00 |
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Pawel Spychalski (DzikuVx)
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b69d1b9ffc
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Renamed hardware pins definitions for LoRa32u4
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2017-10-21 08:15:10 +02:00 |
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Pawel Spychalski (DzikuVx)
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d790d087fe
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Fixed debug flags
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2017-10-20 23:06:14 +02:00 |
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Pawel Spychalski (DzikuVx)
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810abc14eb
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Fixed SPI mode with LoRa32u4 II
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2017-10-20 22:47:46 +02:00 |
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