david.tahir/QuadMeUp_Crossbow
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  • cb3c510815 Further changes to async processing Pawel Spychalski (DzikuVx) 2018-01-02 21:14:11 +01:00
  • 8dfc41759e Another compiler warning fiuxed Pawel Spychalski (DzikuVx) 2018-01-02 20:14:41 +01:00
  • 8071d6ac74 Fixed compiler warnings Pawel Spychalski (DzikuVx) 2017-12-28 12:05:18 +01:00
  • 9d30a69b22 minor change Pawel Spychalski (DzikuVx) 2017-12-24 14:06:34 +01:00
  • 844955ded1 Merge branch 'master' into tx-sbus Pawel Spychalski 2017-12-18 10:19:20 +01:00
  • ac36371cdb cleanup Pawel Spychalski 2017-12-18 10:18:30 +01:00
  • e8f1976a2d async rx mode Pawel Spychalski (DzikuVx) 2017-12-17 09:33:04 +01:00
  • a7c2e13b10 LoRa non-blocking endPacket from https://github.com/sandeepmistry/arduino-LoRa/pull/62 Pawel Spychalski (DzikuVx) 2017-12-16 11:08:39 +01:00
  • 7e9f0fd04e close #36 Pawel Spychalski (DzikuVx) 2017-12-16 10:13:29 +01:00
  • 85461b5d89 close #32 Pawel Spychalski (DzikuVx) 2017-12-16 09:50:02 +01:00
  • 239d1b00e2 Merge branch 'master' into tx-sbus Pawel Spychalski (DzikuVx) 2017-12-16 09:28:54 +01:00
  • 42a0ff3513 Merge pull request #34 from DzikuVx/spi-improvements Paweł Spychalski 2017-12-16 09:26:27 +01:00
  • 931bc59b36 TX happening in single SPI transaction Pawel Spychalski 2017-12-15 14:37:18 +01:00
  • 50e297b3d6 Packet reading is now down in single SPI transaction Pawel Spychalski (DzikuVx) 2017-12-14 23:41:14 +01:00
  • baf8e54d1a Sbus decoding Pawel Spychalski (DzikuVx) 2017-12-14 14:54:17 +01:00
  • c97c5f2b22 Unused property removed Pawel Spychalski (DzikuVx) 2017-12-14 11:56:49 +01:00
  • 65e6521121 Processing improvements Pawel Spychalski (DzikuVx) 2017-12-14 11:55:42 +01:00
  • 37e55a0f47 Fast read implementation Pawel Spychalski 2017-12-06 14:02:08 +01:00
  • 51b7d696af Merge pull request #33 from DzikuVx/local-lora-library Paweł Spychalski 2017-12-01 12:21:06 +01:00
  • 52feecbee8 cleanup Pawel Spychalski 2017-12-01 12:20:41 +01:00
  • 1986f0961b Arduino LoRa library is now part of package Pawel Spychalski 2017-12-01 11:35:09 +01:00
  • 8ffaccbd5f TX power moved to configuration Pawel Spychalski 2017-11-23 14:41:11 +01:00
  • 52daef7667 TX module diagram Pawel Spychalski (DzikuVx) 2017-11-19 13:46:50 +01:00
  • c1867dee9e RSSI buzzer alarms adjusted Pawel Spychalski (DzikuVx) 2017-11-18 17:01:55 +01:00
  • 36b7933f11 Merge pull request #27 from DzikuVx/qsp-callbacks Paweł Spychalski 2017-11-16 20:18:42 +01:00
  • 3778fcd0cd Callback for QSP decoding Pawel Spychalski 2017-11-16 16:12:20 +01:00
  • 9d609dfa77 RX outout table moved to RxDeviceState object Pawel Spychalski 2017-11-16 13:31:29 +01:00
  • 025315489c Merge pull request #26 from DzikuVx/crc-update Paweł Spychalski 2017-11-15 19:09:49 +01:00
  • 9f48e0fd6f Updated CRC method Pawel Spychalski 2017-11-15 11:14:15 +01:00
  • 36dc76db0d Reworked radio handling to early reject false packets Pawel Spychalski (DzikuVx) 2017-11-15 18:53:31 +01:00
  • 149aac3d70 frequency change Pawel Spychalski (DzikuVx) 2017-11-11 22:23:58 +01:00
  • d322447290 Updated radio properties Pawel Spychalski (DzikuVx) 2017-11-11 19:50:38 +01:00
  • 8fc8c20697 All processing moved from ISR to main loop Pawel Spychalski (DzikuVx) 2017-11-11 16:51:00 +01:00
  • 6082f7f4a7 task priority changed Pawel Spychalski (DzikuVx) 2017-11-11 14:09:14 +01:00
  • 1a031aba3f Fixed bug thata was failing to process frames without preamble Pawel Spychalski (DzikuVx) 2017-11-09 19:52:52 +01:00
  • 1057c0995c protocol preamble removed as not required for LoRa packet processing Pawel Spychalski 2017-11-09 14:56:59 +01:00
  • 47f9a37270 diagram for RX module Pawel Spychalski 2017-11-07 13:14:31 +01:00
  • 2b622d0907 Merge branch 'master' of github.com:DzikuVx/QuadMeUp_Crossbow Pawel Spychalski (DzikuVx) 2017-11-05 15:03:53 +01:00
  • 0c9a25d945 RX module schema Pawel Spychalski (DzikuVx) 2017-11-04 09:48:34 +01:00
  • 346ce8234f Delete track2.txt Paweł Spychalski 2017-11-01 12:11:48 +01:00
  • 110b23ce0d Delete track3.txt Paweł Spychalski 2017-11-01 12:11:37 +01:00
  • a1d3b1d3b4 Delete track1.txt Paweł Spychalski 2017-11-01 12:11:26 +01:00
  • 4641d974ac Merge branch 'master' of github.com:DzikuVx/QuadMeUp_Crossbow Pawel Spychalski 2017-11-01 10:18:53 +01:00
  • 5ae986112f Several small fixes for potential race conditions Pawel Spychalski (DzikuVx) 2017-10-30 20:39:32 +01:00
  • 3921cc245c Fixed casting bug on RX side that was causing failsafe to engage without specific reason Pawel Spychalski (DzikuVx) 2017-10-30 17:38:56 +01:00
  • b3d8847d86 OLED RRSI scaling changed to dB Pawel Spychalski (DzikuVx) 2017-10-30 16:35:48 +01:00
  • 34b7a42b85 slower transmission Pawel Spychalski (DzikuVx) 2017-10-29 15:25:36 +01:00
  • b7782db478 Audible alarms on TX side Pawel Spychalski (DzikuVx) 2017-10-29 13:08:39 +01:00
  • 86c7c3af0a Small optimization Pawel Spychalski (DzikuVx) 2017-10-29 09:56:06 +01:00
  • a2fb5abffa Buzzer Single and Continous modes Pawel Spychalski (DzikuVx) 2017-10-29 09:35:00 +01:00
  • b3cac834e2 Reduced number of SPI operations when reading RF packets Pawel Spychalski (DzikuVx) 2017-10-28 23:07:14 +02:00
  • 72cb29eca2 Speed optimization for S.Bus encoding Pawel Spychalski (DzikuVx) 2017-10-28 22:25:38 +02:00
  • 7bb8544880 optimizations for OLED Pawel Spychalski (DzikuVx) 2017-10-28 20:30:56 +02:00
  • 74cb084017 Basic buzzer framework Pawel Spychalski (DzikuVx) 2017-10-28 19:35:06 +02:00
  • d29f76fa7c buzzer processing code Pawel Spychalski (DzikuVx) 2017-10-28 16:55:48 +02:00
  • 9703d3144f Another small optimization to limit resource hogging Pawel Spychalski (DzikuVx) 2017-10-27 13:56:12 +02:00
  • 6277d4cec9 Code cleanup Pawel Spychalski (DzikuVx) 2017-10-27 13:44:01 +02:00
  • 85b1dbe26d performance improvements Pawel Spychalski (DzikuVx) 2017-10-27 13:18:22 +02:00
  • 0f735f0054 close #23 Pawel Spychalski (DzikuVx) 2017-10-27 11:25:48 +02:00
  • 5c090b6868 Fixed race condition that casued concurrent SPI operation and hunged the RX module Pawel Spychalski (DzikuVx) 2017-10-27 09:56:46 +02:00
  • 86f70accff TX module is no longer using interrupts to read from LoRa. This fixes jumpy PPM readouts Pawel Spychalski (DzikuVx) 2017-10-27 07:20:43 +02:00
  • b50564f4bd Default bandwidth increased to 500kHz Pawel Spychalski (DzikuVx) 2017-10-26 20:18:02 +02:00
  • 9ea446de79 Slots for transmitting on RX side close #8 Pawel Spychalski (DzikuVx) 2017-10-26 20:03:20 +02:00
  • 9e0f425ee9 Sloted approach on TX side Pawel Spychalski (DzikuVx) 2017-10-26 16:16:21 +02:00
  • a800031b0a close #15 Pawel Spychalski (DzikuVx) 2017-10-26 13:51:34 +02:00
  • c409214de8 updated SNR scaling Pawel Spychalski (DzikuVx) 2017-10-25 22:03:54 +02:00
  • 0b04e32776 LED blink on RX when receiving, Constant on FAILSAFE Pawel Spychalski (DzikuVx) 2017-10-25 21:34:53 +02:00
  • 429d808fa2 close #10 Pawel Spychalski (DzikuVx) 2017-10-25 21:18:01 +02:00
  • 8f194e3968 close #18 Pawel Spychalski (DzikuVx) 2017-10-25 20:21:13 +02:00
  • 2af594137f scratch update Pawel Spychalski 2017-10-25 12:58:07 +02:00
  • 4e53ebde9c updated sbus rate Pawel Spychalski 2017-10-25 10:59:06 +02:00
  • a6b5946a68 close #12 Pawel Spychalski (DzikuVx) 2017-10-24 21:08:04 +02:00
  • b1c3b36b7c close #20 Pawel Spychalski (DzikuVx) 2017-10-24 20:09:43 +02:00
  • 2a47aac573 close #19 close #13 Pawel Spychalski (DzikuVx) 2017-10-24 20:07:23 +02:00
  • 474d2a9c84 It works. More less Pawel Spychalski (DzikuVx) 2017-10-23 21:16:48 +02:00
  • d0120405fb close #17 Pawel Spychalski (DzikuVx) 2017-10-23 19:37:13 +02:00
  • 974a31ad61 Fixed missing constrain Pawel Spychalski (DzikuVx) 2017-10-23 19:24:50 +02:00
  • 1d16fdd052 close #9 Pawel Spychalski (DzikuVx) 2017-10-23 12:51:05 +02:00
  • 471e532c5a close #16 Pawel Spychalski (DzikuVx) 2017-10-23 12:45:25 +02:00
  • 0a1b5feecd close #1 Pawel Spychalski (DzikuVx) 2017-10-22 20:14:28 +02:00
  • 08b16b4cea close #6 Pawel Spychalski (DzikuVx) 2017-10-22 11:56:17 +02:00
  • 779b64189a close #2 Pawel Spychalski (DzikuVx) 2017-10-22 09:31:46 +02:00
  • 7af49621fc Cleanup Pawel Spychalski (DzikuVx) 2017-10-21 08:48:23 +02:00
  • dcc1a0da34 OLED moved to TX module Pawel Spychalski (DzikuVx) 2017-10-21 08:21:30 +02:00
  • b69d1b9ffc Renamed hardware pins definitions for LoRa32u4 Pawel Spychalski (DzikuVx) 2017-10-21 08:15:10 +02:00
  • d790d087fe Fixed debug flags Pawel Spychalski (DzikuVx) 2017-10-20 23:06:14 +02:00
  • 810abc14eb Fixed SPI mode with LoRa32u4 II Pawel Spychalski (DzikuVx) 2017-10-20 22:47:46 +02:00
  • 021decff98 Rx_health frame encoding, no data is yet acquired from Rx hardware Pawel Spychalski 2017-10-12 13:29:10 +02:00
  • 0071b7880f Store last time frame was received Pawel Spychalski 2017-10-12 10:45:14 +02:00
  • ff2f0f710a RX failsafe with pulling PPM output LOW Pawel Spychalski 2017-10-11 14:40:17 +02:00
  • f0977d0c71 todos Pawel Spychalski (DzikuVx) 2017-10-07 19:31:36 +02:00
  • 01836b8657 another small refactoring Pawel Spychalski (DzikuVx) 2017-10-07 19:06:07 +02:00
  • 022f186175 quite major overhaul Pawel Spychalski (DzikuVx) 2017-10-07 18:57:13 +02:00
  • 3deec452ef refactoring Pawel Spychalski (DzikuVx) 2017-10-07 14:53:50 +02:00
  • 5b5ca9fedf methods to read RSSI and SNR Pawel Spychalski (DzikuVx) 2017-10-07 12:10:15 +02:00
  • 13add24fc7 RX devide Listens Before Talk Pawel Spychalski 2017-10-06 14:38:40 +02:00
  • 3395587580 Defines refactoring Pawel Spychalski 2017-10-06 13:47:42 +02:00
  • 8d5cf2144f Merge branch 'master' of github.com:DzikuVx/QuadMeUp_Crossbow Pawel Spychalski 2017-10-05 09:44:31 +02:00
  • 1632baccc8 Temprary table used during PPM decoding Pawel Spychalski 2017-10-05 09:43:59 +02:00
  • 4bc7668ae9 Support for SPI connected SX1278 Pawel Spychalski (DzikuVx) 2017-09-30 18:43:03 +02:00