Pawel Spychalski (DzikuVx)
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d29f76fa7c
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buzzer processing code
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2017-10-28 16:55:48 +02:00 |
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Pawel Spychalski (DzikuVx)
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9703d3144f
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Another small optimization to limit resource hogging
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2017-10-27 13:56:12 +02:00 |
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Pawel Spychalski (DzikuVx)
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6277d4cec9
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Code cleanup
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2017-10-27 13:44:01 +02:00 |
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Pawel Spychalski (DzikuVx)
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85b1dbe26d
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performance improvements
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2017-10-27 13:18:22 +02:00 |
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Pawel Spychalski (DzikuVx)
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0f735f0054
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close #23
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2017-10-27 11:25:48 +02:00 |
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Pawel Spychalski (DzikuVx)
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5c090b6868
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Fixed race condition that casued concurrent SPI operation and hunged the RX module
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2017-10-27 09:56:46 +02:00 |
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Pawel Spychalski (DzikuVx)
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86f70accff
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TX module is no longer using interrupts to read from LoRa. This fixes jumpy PPM readouts
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2017-10-27 07:20:43 +02:00 |
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Pawel Spychalski (DzikuVx)
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b50564f4bd
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Default bandwidth increased to 500kHz
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2017-10-26 20:18:02 +02:00 |
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Pawel Spychalski (DzikuVx)
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9ea446de79
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Slots for transmitting on RX side close #8
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2017-10-26 20:03:20 +02:00 |
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Pawel Spychalski (DzikuVx)
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9e0f425ee9
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Sloted approach on TX side
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2017-10-26 16:16:21 +02:00 |
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Pawel Spychalski (DzikuVx)
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a800031b0a
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close #15
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2017-10-26 13:51:34 +02:00 |
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Pawel Spychalski (DzikuVx)
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c409214de8
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updated SNR scaling
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2017-10-25 22:03:54 +02:00 |
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Pawel Spychalski (DzikuVx)
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0b04e32776
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LED blink on RX when receiving, Constant on FAILSAFE
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2017-10-25 21:34:53 +02:00 |
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Pawel Spychalski (DzikuVx)
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429d808fa2
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close #10
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2017-10-25 21:18:01 +02:00 |
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Pawel Spychalski (DzikuVx)
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8f194e3968
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close #18
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2017-10-25 20:21:13 +02:00 |
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Pawel Spychalski
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4e53ebde9c
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updated sbus rate
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2017-10-25 10:59:06 +02:00 |
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Pawel Spychalski (DzikuVx)
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a6b5946a68
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close #12
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2017-10-24 21:08:04 +02:00 |
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Pawel Spychalski (DzikuVx)
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b1c3b36b7c
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close #20
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2017-10-24 20:09:43 +02:00 |
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Pawel Spychalski (DzikuVx)
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2a47aac573
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close #19 close #13
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2017-10-24 20:07:23 +02:00 |
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Pawel Spychalski (DzikuVx)
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474d2a9c84
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It works. More less
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2017-10-23 21:16:48 +02:00 |
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Pawel Spychalski (DzikuVx)
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d0120405fb
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close #17
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2017-10-23 19:37:13 +02:00 |
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Pawel Spychalski (DzikuVx)
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974a31ad61
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Fixed missing constrain
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2017-10-23 19:24:50 +02:00 |
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Pawel Spychalski (DzikuVx)
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1d16fdd052
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close #9
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2017-10-23 12:51:05 +02:00 |
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Pawel Spychalski (DzikuVx)
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471e532c5a
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close #16
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2017-10-23 12:45:25 +02:00 |
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Pawel Spychalski (DzikuVx)
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0a1b5feecd
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close #1
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2017-10-22 20:14:28 +02:00 |
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Pawel Spychalski (DzikuVx)
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08b16b4cea
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close #6
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2017-10-22 11:56:17 +02:00 |
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Pawel Spychalski (DzikuVx)
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779b64189a
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close #2
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2017-10-22 09:31:46 +02:00 |
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Pawel Spychalski (DzikuVx)
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7af49621fc
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Cleanup
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2017-10-21 08:48:23 +02:00 |
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Pawel Spychalski (DzikuVx)
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dcc1a0da34
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OLED moved to TX module
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2017-10-21 08:21:30 +02:00 |
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Pawel Spychalski (DzikuVx)
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b69d1b9ffc
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Renamed hardware pins definitions for LoRa32u4
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2017-10-21 08:15:10 +02:00 |
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Pawel Spychalski (DzikuVx)
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d790d087fe
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Fixed debug flags
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2017-10-20 23:06:14 +02:00 |
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Pawel Spychalski (DzikuVx)
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810abc14eb
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Fixed SPI mode with LoRa32u4 II
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2017-10-20 22:47:46 +02:00 |
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Pawel Spychalski
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021decff98
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Rx_health frame encoding, no data is yet acquired from Rx hardware
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2017-10-12 13:29:10 +02:00 |
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Pawel Spychalski
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0071b7880f
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Store last time frame was received
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2017-10-12 10:45:14 +02:00 |
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Pawel Spychalski
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ff2f0f710a
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RX failsafe with pulling PPM output LOW
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2017-10-11 14:40:17 +02:00 |
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Pawel Spychalski (DzikuVx)
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f0977d0c71
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todos
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2017-10-07 19:31:36 +02:00 |
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Pawel Spychalski (DzikuVx)
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01836b8657
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another small refactoring
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2017-10-07 19:06:07 +02:00 |
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Pawel Spychalski (DzikuVx)
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022f186175
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quite major overhaul
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2017-10-07 18:57:13 +02:00 |
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Pawel Spychalski (DzikuVx)
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3deec452ef
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refactoring
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2017-10-07 14:53:50 +02:00 |
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Pawel Spychalski (DzikuVx)
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5b5ca9fedf
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methods to read RSSI and SNR
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2017-10-07 12:10:15 +02:00 |
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Pawel Spychalski
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13add24fc7
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RX devide Listens Before Talk
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2017-10-06 14:38:40 +02:00 |
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Pawel Spychalski
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3395587580
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Defines refactoring
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2017-10-06 13:47:42 +02:00 |
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Pawel Spychalski
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8d5cf2144f
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Merge branch 'master' of github.com:DzikuVx/QuadMeUp_Crossbow
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2017-10-05 09:44:31 +02:00 |
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Pawel Spychalski
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1632baccc8
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Temprary table used during PPM decoding
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2017-10-05 09:43:59 +02:00 |
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Pawel Spychalski (DzikuVx)
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4bc7668ae9
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Support for SPI connected SX1278
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2017-09-30 18:43:03 +02:00 |
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Pawel Spychalski (DzikuVx)
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7b5bf4d0e2
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Merge branch 'master' of github.com:DzikuVx/QuadMeUp_Crossbow
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2017-09-30 16:21:58 +02:00 |
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Pawel Spychalski (DzikuVx)
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8c3199a60f
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readme update
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2017-09-30 16:21:52 +02:00 |
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Pawel Spychalski
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6497845aec
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RC_DATA decoding
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2017-09-28 15:25:46 +02:00 |
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Pawel Spychalski
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2559bd8bc2
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some more work
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2017-09-28 13:17:01 +02:00 |
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Pawel Spychalski (DzikuVx)
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a95dab355b
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minor changes
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2017-09-27 22:38:02 +02:00 |
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