Commit Graph

36 Commits

Author SHA1 Message Date
Pawel Spychalski (DzikuVx)
a6b5946a68 close #12 2017-10-24 21:08:04 +02:00
Pawel Spychalski (DzikuVx)
b1c3b36b7c close #20 2017-10-24 20:09:43 +02:00
Pawel Spychalski (DzikuVx)
2a47aac573 close #19 close #13 2017-10-24 20:07:23 +02:00
Pawel Spychalski (DzikuVx)
474d2a9c84 It works. More less 2017-10-23 21:16:48 +02:00
Pawel Spychalski (DzikuVx)
d0120405fb close #17 2017-10-23 19:37:13 +02:00
Pawel Spychalski (DzikuVx)
974a31ad61 Fixed missing constrain 2017-10-23 19:24:50 +02:00
Pawel Spychalski (DzikuVx)
1d16fdd052 close #9 2017-10-23 12:51:05 +02:00
Pawel Spychalski (DzikuVx)
471e532c5a close #16 2017-10-23 12:45:25 +02:00
Pawel Spychalski (DzikuVx)
0a1b5feecd close #1 2017-10-22 20:14:28 +02:00
Pawel Spychalski (DzikuVx)
08b16b4cea close #6 2017-10-22 11:56:17 +02:00
Pawel Spychalski (DzikuVx)
779b64189a close #2 2017-10-22 09:31:46 +02:00
Pawel Spychalski (DzikuVx)
7af49621fc Cleanup 2017-10-21 08:48:23 +02:00
Pawel Spychalski (DzikuVx)
dcc1a0da34 OLED moved to TX module 2017-10-21 08:21:30 +02:00
Pawel Spychalski (DzikuVx)
b69d1b9ffc Renamed hardware pins definitions for LoRa32u4 2017-10-21 08:15:10 +02:00
Pawel Spychalski (DzikuVx)
d790d087fe Fixed debug flags 2017-10-20 23:06:14 +02:00
Pawel Spychalski (DzikuVx)
810abc14eb Fixed SPI mode with LoRa32u4 II 2017-10-20 22:47:46 +02:00
Pawel Spychalski
021decff98 Rx_health frame encoding, no data is yet acquired from Rx hardware 2017-10-12 13:29:10 +02:00
Pawel Spychalski
0071b7880f Store last time frame was received 2017-10-12 10:45:14 +02:00
Pawel Spychalski
ff2f0f710a RX failsafe with pulling PPM output LOW 2017-10-11 14:40:17 +02:00
Pawel Spychalski (DzikuVx)
f0977d0c71 todos 2017-10-07 19:31:36 +02:00
Pawel Spychalski (DzikuVx)
01836b8657 another small refactoring 2017-10-07 19:06:07 +02:00
Pawel Spychalski (DzikuVx)
022f186175 quite major overhaul 2017-10-07 18:57:13 +02:00
Pawel Spychalski (DzikuVx)
3deec452ef refactoring 2017-10-07 14:53:50 +02:00
Pawel Spychalski (DzikuVx)
5b5ca9fedf methods to read RSSI and SNR 2017-10-07 12:10:15 +02:00
Pawel Spychalski
13add24fc7 RX devide Listens Before Talk 2017-10-06 14:38:40 +02:00
Pawel Spychalski
3395587580 Defines refactoring 2017-10-06 13:47:42 +02:00
Pawel Spychalski
8d5cf2144f Merge branch 'master' of github.com:DzikuVx/QuadMeUp_Crossbow 2017-10-05 09:44:31 +02:00
Pawel Spychalski
1632baccc8 Temprary table used during PPM decoding 2017-10-05 09:43:59 +02:00
Pawel Spychalski (DzikuVx)
4bc7668ae9 Support for SPI connected SX1278 2017-09-30 18:43:03 +02:00
Pawel Spychalski
6497845aec RC_DATA decoding 2017-09-28 15:25:46 +02:00
Pawel Spychalski
2559bd8bc2 some more work 2017-09-28 13:17:01 +02:00
Pawel Spychalski (DzikuVx)
a95dab355b minor changes 2017-09-27 22:38:02 +02:00
Pawel Spychalski (DzikuVx)
458ee9233a Correct way of encoding RC_DATA frame 2017-09-27 22:16:15 +02:00
Pawel Spychalski (DzikuVx)
3f0fb692ab encoding of RC_DATA frame 2017-09-27 20:38:37 +02:00
Pawel Spychalski (DzikuVx)
b338ba959a RC_DATA frame encoded 2017-09-24 12:05:21 +02:00
Pawel Spychalski (DzikuVx)
6f375eafb6 QSP protocol implementation 2017-09-23 20:44:27 +02:00